1. Field of the Invention
The present invention relates to an electrostatic damage protection circuit provided in a semiconductor integrated device to prevent an electrostatic breakdown.
2. Description of the Related Art
Recently, field effect transistors have been formed on an SOI substrate (an SOI-FET) instead on a conventional bulk semiconductor substrate. The SOI-FET is formed in the thin silicon layer (the SOI layer) formed on the insulating layer. Since the SOI-FET is perfectly isolated by the insulating layer and an isolating layer (a field layer), a parasitic capacitance of the SOI-FET is reduced. The insulating layer is for example, a buried oxide layer (a BOX layer). And, since a body region is fully or partly depleted due to the thin SOI layer, the SOI-FET can have a precipitous or steep sub-threshold characteristic. Therefore, the SOI-FET can operate with high speed and improved power savings. Also, since formation of a parasitic bipolar is prevented due to the perfectly isolated structure, latch up can be inhibited. The body region is P type when the SOI-FET is a NMOS transistor, and is a N type when the SOI-FET is PMOS transistor.
By the way, a kink phenomenon is well known as one of the demerits of the SOI-FET. Since a body voltage rises when a drain potential rises, a bipolar current increases. Therefore, a drain current increases. Such a phenomenon is called the kink phenomenon. This kink phenomenon is typical of the SOI-FET which has a floating body region. As a countermeasure against such kink phenomenon, a body contact method is well known such that the body voltage is fixed.
FIG. 16 is a plan view showing the structure of a conventional NMOS transistor which is a body contact type having an electrostatic breakdown protection circuit. A gate electrode 60G crosses over an N type impurity region 60N which includes source and drain regions, and is connected to a metal wiring 60M which supplies a gate potential, through a contact hole 61C. One end of the gate electrode 60G overlaps a P type impurity region 60P, which has an opposite conductive type as that of the source and drain regions 60N. The P type impurity region 60P is connected to a metal wiring 63M which supplies a body potential, through contact holes 60C. A metal wiring 61M supplies a source potential. A metal wiring 62M supplies a drain potential. As a result, since the body voltage is fixed to the source potential or a negative potential, the kink phenomenon in the NMOS transistor can be inhibited.
Recently, a dynamic threshold MOS (DTMOS) which is one of the body contact type MOS transistors has been considered. FIG. 17 is a plan view showing a conventional DTMOS transistor having an electrostatic breakdown protection circuit. A gate electrode 70G crosses over an N type impurity region 70N which includes source and drain regions, and is connected to a metal wiring 70M which supplies a gate potential, through a contact hole 71C. The metal wiring 70M overlaps with the gate electrode 70G and extends along the gate electrode 70G. One end of the gate electrode 70G overlaps a P type impurity region 70P which has an opposite conductive type than that of the source and drain regions 70N. The P type impurity region 70P is connected to the metal wiring 70M through contact holes 70C. A metal wiring 71M supplies a source potential. A metal wiring 72M supplies a drain potential. As a result, since a threshold voltage falls due to a bias effect occurring when the gate voltage is applied, the DTMOS transistor can operate at a low power and with high speed.
By the way, an output transistor (an output buffer) which has a wide gate width in general, is located at an output terminal of a semiconductor integrated device. Since a surge (e.g., a static electricity) may be applied to the output terminal, a protection transistor having a gate electrode fixed to a source potential (the gate electrode is an OFF state), is connected in parallel with the output transistor. Therefore, an electrostatic breakdown protection property against the electrostatic surge is improved.
Next, an operation of the DTMOS transistor which consists of an NMOS transistor will be described below. Since the body potential rises due to a breakdown occurring when the electrostatic surge is applied from the drain region, a potential between the body region and the source region becomes forward biased. As a result, a surge current flows to the source region due to a bipolar operation. At that time, since the gate voltage also rises in concurrence with the breakdown, a channel forms in a boundary face of the body region. As a result, since a base current increases due to carrier recombination, bipolar operation is able to occur the bipolar operation effectively.
As shown in FIG. 17, in the conventional DTMOS transistor, since the P type impurity region 70P which fixes the body potential is located at one end of the N type impurity region 70N, a response for each of the DTMOS transistors which are formed in the same active region differs. In addition, the output transistor has the wide gate width, so that protection against the electrostatic breakdown more difficult.